| A clock design in a FPGA written mostly in VHDL. I have two designs available. Both are synthesized to a Altera MAX FPGA EPM1270T144C5, JTAG...
| A clock design in a FPGA written mostly in VHDL. I have two designs available. Both are synthesized to a Altera MAX FPGA EPM1270T144C5, JTAG...